In the manufacture of various products, electrically conductive material (typically a metal, such as aluminum or copper) and dielectric material (often, a silicon dioxide-based material) are formed on, in, or as part of, a substrate such that regions of the electrically conductive material are separated by regions of dielectric material from other regions of the electrical conductive material to define electrical elements (e.g., transistors, capacitors, resistors) and electrical interconnections between electrical elements. (For convenience, a substrate including—i.e., having as part of, or having formed on or in—electrically conductive regions separated by a dielectric region is sometimes referred to herein as an “electronic device”). Electronic components (microprocessors, memory chips, etc.) for computers and other devices are well-known examples of such products. Other products too, such as flat panel displays, can also be constructed in that way.
During operation of an electronic device, the flow of current through an electrical interconnection can cause electromigration (i.e., movement of atoms of an electrically conductive material as a result of current flow through the electrically conductive material) which can result in deformation of the electrical interconnection (e.g., formation of voids, hillocks and/or extrusions), in particular at interface(s) with adjacent material. Such deformation can result in undesirable current leakage or current flow inhibition. As the characteristic dimension of electrical interconnections of electronic devices becomes smaller (the manufacture of a variety of electronic devices now requires the cost-effective production of electrical interconnections having a characteristic dimension at the sub-100 nm size scale, and those required in future electronic devices will be increasingly smaller), the increased current density flowing through those electrical interconnections renders electromigration even more of a problem.
FIG. 1A is a simplified cross-sectional view of part of a semiconductor device 100, illustrating electrically conductive regions 110 separated by dielectric regions 120. (A semiconductor device is an electronic device in which the substrate is made of, in whole or in functionally significant part, a semiconductor material or materials.) The electrically conductive regions 110 and dielectric regions 120 are formed over (i.e., formed subsequent to, and through a common axis or axes perpendicular to the layers of material formed in a device) another electrically conductive region 105. The electrically conductive regions 110 can be, for example, interconnections between the electrically conductive region 105 and other electrically conductive material to be subsequently formed as part of the semiconductor device 100. In current semiconductor devices, copper is commonly used to form electrically conductive regions and a silicon dioxide-based material (e.g., FSG, SiCOH, porous SiCOH, MSQ) is commonly used to form dielectric regions. Additionally, in current semiconductor devices, the dielectric region often includes a hard mask layer (which is often formed of a silicon-based—e.g., SiCx, SiNx, SiCxNy— material) formed at the top (i.e., the surface of a region on which material can be formed during subsequent processing of a device after formation of the region) of the dielectric region: in FIG. 1A—and FIG. 1B, discussed below—the semiconductor device 100 is illustrated with a hard mask layer 120a formed at the top of each of the dielectric regions 120.
FIG. 1B is a simplified cross-sectional view of the part of a semiconductor device 100, illustrating a dielectric barrier layer 130 formed on the electrically conductive regions 110 and dielectric regions 120. (In FIGS. 1A and 1B, a dielectric barrier layer 106 previously formed on the electrically conductive region 105 of the semiconductor device 100 is also illustrated.) A “dielectric barrier layer” is a layer of dielectric material in a semiconductor (or other electronic) device that is formed non-selectively on both electrically conductive regions and dielectric regions that separate those electrically conductive regions, after planarization of the top of the electrically conductive regions and dielectric regions, to inhibit diffusion of material from the electrically conductive regions into adjacent regions (in particular, into dielectric material subsequently formed over the electrically conductive regions) of the semiconductor device. (A dielectric barrier layer is also sometimes referred to as a “via etch stop layer”, a “dielectric cap”, or a “capping layer”. Herein, the term “dielectric barrier layer” is used; as discussed in more detail elsewhere herein, “capping layer” is used to refer to a different type of layer, which may, nevertheless, provide functionality associated with a dielectric barrier layer, such as inhibition of diffusion of material from electrically conductive regions.) In current semiconductor devices, compositions including silicon together with carbon and/or nitrogen (i.e., SiCx, SiNx, SiCxNy) are commonly used to form a dielectric barrier layer. Since these materials have a higher dielectric constant than the dielectric materials that could otherwise be used (i.e., if it was not necessary or desirable to inhibit diffusion from the electrically conductive regions), an undesirable consequence of the presence of a dielectric barrier layer is that the capacitance associated with the structure illustrated in FIG. 1B is increased, which can increase power consumption and/or decrease speed of operation of the semiconductor device. Further, current common implementations of a dielectric barrier layer do not adhere well to current common implementations of electrically conductive regions in semiconductor devices and, consequently, do little to inhibit electromigration in the electrically conductive regions, which commonly is initiated at the interface between the electrically conductive regions and the dielectric barrier layer. In view of the foregoing, there is a need for improved inhibition of electromigration in electrically conductive regions (and, in particular, at interface(s) of electrically conductive regions with adjacent regions formed of other material) of semiconductor (and other electronic) devices. There is also a need for reduction in capacitance of the structure formed in the vicinity of the electrically conductive regions of semiconductor (and other electronic) devices, while adequately maintaining a barrier to diffusion of material from the electrically conductive regions into adjacent regions formed of other material. These needs have—and will continue to—become increasingly strong as the characteristic dimension of features (e.g., electrical interconnections) in electronic devices becomes smaller.
To inhibit electromigration at the interface between electrically conductive regions and a dielectric barrier layer of a semiconductor device, a layer of material has been selectively formed on the electrically conductive regions before forming the dielectric barrier layer. (“Selective” formation of a material on a region or surface means that the material forms on that region or surface with better coverage of the region or surface than that with which the material forms on other region(s) or surface(s).) Such a selectively formed layer can be referred to as, for example, a “capping layer” or a “self-aligned barrier layer”; herein, the former term is generally used. Selective formation of a capping layer on electrically conductive regions is illustrated in FIGS. 2A through 2C. FIG. 2A is a simplified cross-sectional view of part of a semiconductor device 200, illustrating electrically conductive regions 210 separated by a dielectric region 220. FIG. 2B is a simplified cross-sectional view of the part of a semiconductor device 200, illustrating the selective formation of a capping layer 240 on the electrically conductive regions 210, but not the dielectric region 220. FIG. 2C is a simplified cross-sectional view of the part of a semiconductor device 200, illustrating a dielectric barrier layer 230 formed on the capping layer 240 and the dielectric region 220. Several ways of selectively forming the capping layer 240 have been tried, using various materials and processes.
For example, a capping layer has been formed by selectively depositing an appropriate material on electrically conductive regions. A metallic material is often used because metallic materials have the properties necessary to catalyze growth of a layer on copper, which is commonly used to form the electrically conductive regions. For instance, electroless deposition has been used to selectively deposit a metal alloy (e.g., an alloy of cobalt, tungsten and phosphorous; an alloy of cobalt and boron; or an alloy of nickel, molybdenum and phosphorous) on copper regions. An approach of this type is described in “High Reliability Cu Interconnection Utilizing a Low Contamination CoWP Capping Layer”, by T. Ishigami et al., Proceedings of the 2004 IEEE International Interconnect Technology Conference, Jun. 7-9, 2004, pp. 75-77, the disclosure of which is hereby incorporated by reference herein. Or, for instance, chemical vapor deposition has been used to selectively deposit tungsten on copper regions. An approach of this type is described in “A Robust, Deep-Submicron Copper Interconnect Structure using Self-Aligned Metal Capping Method”, by T. Saito et al., Proceedings of the 2004 IEEE International Interconnect Technology Conference, Jun. 7-9, 2004, pp. 36-38, the disclosure of which is hereby incorporated by reference herein. However, the selectivity of these approaches is inadequate to inhibit formation of capping layer material (which is electrically conductive) on dielectric region(s) (in FIGS. 2B and 2C, a thin layer of capping layer material—not designated by a numeral in FIGS. 2B and 2C—is shown on the dielectric region 220) to an extent that prevents unacceptable current leakage between electrically conductive regions separated by those dielectric region(s) (this is particularly so as the characteristic dimension of electrical interconnections of electronic devices becomes smaller). This may be due, at least in part, because residual material from the electrically conductive regions that is left on the dielectric region(s) after planarization (e.g., chemical mechanical polishing) of the exposed surfaces of the electrically conductive regions and dielectric region(s) provides nucleation sites for the capping layer material (which is chosen for its affinity for forming on the material of the electrically conductive regions), significantly reducing preferential formation of the capping layer material on the electrically conductive regions as compared to the dielectric region(s).
A capping layer has also been formed by chemically modifying a top part of each of the electrically conductive regions. For example, a capping layer has been formed by chemically modifying the top parts of copper regions using silicidation and nitridation (this can be accomplished using wet or dry processing). An approach of this type is described in “Integration and performance of an alternative approach using copper silicide as a self-aligned barrier for 45 nm technology node Cu interconnects”, by L. G. Gosset et al., Proceedings of the 2004 IEEE International Interconnect Technology Conference, Jun. 7-9, 2004, pp. 15-17, the disclosure of which is hereby incorporated by reference herein. However, the capping layer formed in this way undesirably increases resistance in the electrically conductive regions.
It has also been proposed to form a layer of organic material on electrically conductive regions of a semiconductor device to inhibit electromigration at the surfaces of the electrically conductive regions. (Such an organic layer can also be referred to as a “capping layer”). The use of organic material, which is a very poor electrical conductor, eliminates the potential for unacceptable current leakage between electrically conductive regions resulting from the presence of the capping layer, even if the process(es) and material(s) used to form the organic layer are not particularly selective in preferentially forming the organic layer on electrically conductive regions. U.S. Patent Application Publication No. US 2004/0203192 describes such an approach in which a self-assembled organic monolayer (in particular, a thiolate self-assembled monolayer) is covalently bonded to metallic regions. However, it is believed that the thiolate self-assembled monolayers described therein may not produce, when formed on copper (as discussed above, a material commonly used to form electrically conductive regions of a semiconductor device), a thermally stable capping layer that remains continuous and defect-free (i.e., having sufficiently few defects according to one or more criteria) under operating conditions of the semiconductor device, and therefore may not adequately inhibit electromigration, or provide an adequate copper diffusion barrier that can enable elimination of the dielectric barrier layer from the semiconductor device.